Things that need to be twaked/improved: cache

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omarsis81
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Things that need to be twaked/improved: cache

Post by omarsis81 »

I run SpeedSys in a real 430VX motherboard with a Pentium MMX 233 and then compared with PCem11. Big surprise! L1 is way out of scale compared to real microprocessor.
Pentiums MMX have 16 kb L1 for data (what is measured by SpeedSys). PCem, reports 64 kb using "a little" cache; 128 kb using "a bit" and 256 kb selecting "some" and a hilarious 512 kb on "a lot".

First pic, real hardware.
Second, PCem 11
VD_233-ConvertImage.jpg
VD_233-ConvertImage.jpg (70.63 KiB) Viewed 3725 times
speedsys1-little.jpg
speedsys1-little.jpg (111.06 KiB) Viewed 3726 times


Regarding, L2 or motherboard cache things get more obscure: SpeedSys detects the following L2 based on each cache configuration
Case 1, little cache, 128 kb
Case 2, a bit cache, 256 kb
Case 3, some, 512 kb

Fine so far, however, SiSoft Sandra 2001 can't detect any L2 cache (I tried each PCem's cache configuration, none works)
Of course, in my real motheboard it detects 512 kb L2 cache
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omarsis81
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Re: Things that need to be twaked/improved: cache

Post by omarsis81 »

boot.jpg
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Also, in the boot screen it doesn't detect any L2 cache either
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omarsis81
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Re: Things that need to be twaked/improved: cache

Post by omarsis81 »

In my opinion, L1 should be hardcoded and shouldn't be allowed to be altered, 16+16 kb on the Pentium MMX. You can, however, provide different options for L2 motherboard cache, 128, 256, 512, 1 or 2MB.

Thank you, and sorry for the long post
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SarahWalker
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Re: Things that need to be twaked/improved: cache

Post by SarahWalker »

The cache emulation is complete garbage, and I would have removed it if I hadn't had numerous people asking me not to. It isn't possible to do even remotely accurate cache emulation without destroying emulator performance.
Battler
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Re: Things that need to be twaked/improved: cache

Post by Battler »

- omarsis81: The L2 cache detection depends on the emulated boards. I've been testing the emulation of some ASUS boards that I have BIOS'es and datasheets of, for about a year now, they seem to detect 512 kB L2 cache and consequently have insanely fast I/O - so fast that the POST screen flies by so fast that it's VERY difficult to get into Setup.
Of course, the L2 cache appears as none on any board that's present in mainline PCem. Now I wonder why some BIOS'es detect so much of it.
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omarsis81
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Re: Things that need to be twaked/improved: cache

Post by omarsis81 »

SarahWalker wrote:The cache emulation is complete garbage, and I would have removed it if I hadn't had numerous people asking me not to. It isn't possible to do even remotely accurate cache emulation without destroying emulator performance.
I believe the goal of every emulator is to be a close to the real thing as possible, so I wouldn´t mind some perfomance loss as long as the cache system works fine.
Another option could be to have more profiles for caches, like the ones we have now plus one or two more profile entries, like

- a little
- a bit
- some
- a lot
- inifine
- real emulation w/ 512 kb
- real emulation w/ 1024 kb
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SarahWalker
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Re: Things that need to be twaked/improved: cache

Post by SarahWalker »

I don't think you'd tolerate the performance loss this would cause.
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omarsis81
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Re: Things that need to be twaked/improved: cache

Post by omarsis81 »

SarahWalker wrote:I don't think you'd tolerate the performance loss this would cause.
Could it be possible to have the cache system on a dedicated thread?
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SarahWalker
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Re: Things that need to be twaked/improved: cache

Post by SarahWalker »

Er, no. As impossible as splitting the CPU emulation over multiple threads.
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