Currently all of the DX4/x5 processors are identified as write-through with no write-back models available
My AM5x86-133 was a write-back, and benched better in Speedsys than PCem at the same clock rate (160mhz) so i wonder if that has anything to do with it.
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My guess is that is part of the unemulated cache system currently implemented
I can have a look at why it's identifying as write-through, but as PCem has no cache emulation it will have no impact in performance.
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