[PATCH] Memory patch

Discussion of development and patch submission.
Battler
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[PATCH] Memory patch

Postby Battler » Tue 15 Dec, 2015 6:12 pm

The patch is attached. Makes sure the romext mapping is only enabled for BIOS'es that use XTIDE or ATIDE.
Attachments
pcem_mem.patch
(869 Bytes) Downloaded 53 times
SarahWalker
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Re: [PATCH] Memory patch

Postby SarahWalker » Mon 04 Jan, 2016 8:30 pm

I think the best approach would be to move the mapping and ROM loading for this to xtide.c, in the same way as it's handled for the video cards. Hence I probably won't take this patch.

Does disabling the mapping fix anything, or is this change only for neatness?
Battler
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Joined: Sun 06 Jul, 2014 7:05 pm

Re: [PATCH] Memory patch

Postby Battler » Mon 04 Jan, 2016 9:39 pm

It's just to make sure unused mappings aren't active when they don't need to be.
Greatpsycho
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Re: [PATCH] Memory patch

Postby Greatpsycho » Fri 13 Oct, 2017 12:29 pm

This patch improves accuracy when word/dword/qword memory accessing at addresses across page or segment boundaries.
Attachments
mem.c.patch
Patch for improve memory access.
(3.44 KiB) Downloaded 6 times
SarahWalker
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Re: [PATCH] Memory patch

Postby SarahWalker » Fri 13 Oct, 2017 7:02 pm

Is this something which is actually causing problems? IIRC readmem*/writemem* are already catering for the problematic misalignment cases.
Greatpsycho
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Re: [PATCH] Memory patch

Postby Greatpsycho » Fri 13 Oct, 2017 10:27 pm

SarahWalker wrote:Is this something which is actually causing problems? IIRC readmem*/writemem* are already catering for the problematic misalignment cases.


I have not yet experienced a problem in almost all usual cases. However, I have written this patch because I think there may be a problem in a few unusual cases(i.e. EMS memory access at accrossing EMS page).
SarahWalker
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Re: [PATCH] Memory patch

Postby SarahWalker » Sat 14 Oct, 2017 8:31 am

Accesses that cross a page should be catered for, see for example in writememll() :

Code: Select all

 if (addr2 & 3)
        {
                if (!cpu_cyrix_alignment || (addr2 & 7) > 4)
                        cycles -= timing_misaligned;
                if ((addr2 & 0xFFF) > 0xFFC)
                {
                        /*Crossing a page here...*/
                        if (cr0>>31)
                        {
                                if (mmutranslate_write(addr2)   == 0xffffffff) return;
                                if (mmutranslate_write(addr2+3) == 0xffffffff) return;
                        }
                        writememwl(seg,addr,val);
                        writememwl(seg,addr+2,val>>16);
                        return;
                }
                else if (writelookup2[addr2 >> 12] != -1)
                {
                        *(uint32_t *)(writelookup2[addr2 >> 12] + addr2) = val;
                        return;
                }
        }

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