Optional: Hacky Pentium support

[Alegend45]

After going over the various attributes of instructions on the Pentium, I seem to have successfully duplicated most of the timings of the Pentium while keeping compatibility with the 430VX bios. As a result, I can now run ridiculously kludgy Pentium emulation in PCem. And yes, the U and V pipes are emulated. I only really paid attention to the P5 microarchitecture, though I could probably extend this to pretty much all P5 variants except for P55C, or the architecture of the Pentium MMX.

Code: Select all

diff -r f18f3527baad src/cpu.c
--- a/src/cpu.c	Wed Nov 05 21:27:56 2014 +0000
+++ b/src/cpu.c	Sat Nov 08 23:55:25 2014 -0600
@@ -22,6 +22,8 @@
 int cpu_hasMMX, cpu_hasMSR;
 int cpu_hasCR4;
 
+int isp5;
+
 uint64_t cpu_CR4_mask;
 
 uint64_t tsc = 0;
@@ -249,6 +251,14 @@
         {"",             -1,        0, 0, 0}
 };
 
+CPU cpus_P5[] =
+{
+        /*Intel P5 Pentium*/
+        {"Pentium 60",  CPU_P5, 6, 60000000, 1, 0x525, 0x525, 0},
+        {"Pentium 66",  CPU_P5, 6, 66000000, 1, 0x525, 0x525, 0},
+        {"",             -1,         0, 0, 0}
+};
+
 void cpu_set_edx()
 {
         EDX = models[model].cpu[cpu_manufacturer].cpus[cpu].edx_reset;
@@ -263,6 +273,7 @@
         is8086   = (cpu_s->cpu_type >= CPU_8088);
         is486    = (cpu_s->cpu_type >= CPU_i486SX) || (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC);
         hasfpu   = (cpu_s->cpu_type >= CPU_i486DX);
+        isp5     = (cpu_s->cpu_type == CPU_P5);
         cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86);
         cpu_16bitbus = (cpu_s->cpu_type == CPU_386SX || cpu_s->cpu_type == CPU_486SLC);
         if (cpu_s->multi) 
@@ -433,6 +444,24 @@
                 cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
                 break;
                 
+                case CPU_P5:
+                timing_rr = 1;
+                timing_rm = 1;
+                timing_mr = 1;
+                timing_mm = 1; //Not known if this is actually a thing on the Pentium.
+                timing_rml = 1;
+                timing_mrl = 1;
+                timing_mml = 1;
+                //Both of these will need updating if you want to emulate the branch predictor. Wikipedia says it uses a saturating counter.
+                timing_bt = 1;
+                timing_bnt = 1+3; //The plus 3 is for branch misprediction.
+                cpu_hasrdtsc = 1;
+                msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
+                cpu_hasMSR = 1;
+                cpu_hasCR4 = 1;
+                cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
+                break;
+                
                 default:
                 fatal("cpu_set : unknown CPU type %i\n", cpu_s->cpu_type);
         }
@@ -443,6 +472,7 @@
         switch (models[model].cpu[cpu_manufacturer].cpus[cpu].cpu_type)
         {
                 case CPU_i486DX:
+                case CPU_P5:
                 if (!EAX)
                 {
                         EAX = 0x00000001;
diff -r f18f3527baad src/cpu.h
--- a/src/cpu.h	Wed Nov 05 21:27:56 2014 +0000
+++ b/src/cpu.h	Sat Nov 08 23:55:25 2014 -0600
@@ -24,6 +24,7 @@
 
 /*586 class CPUs*/
 #define CPU_WINCHIP 14
+#define CPU_P5 15
 
 #define MANU_INTEL 0
 #define MANU_AMD   1
@@ -60,6 +61,7 @@
 extern CPU cpus_Am486[];
 extern CPU cpus_Cx486[];
 extern CPU cpus_WinChip[];
+extern CPU cpus_P5[];
 
 extern CPU cpus_pcjr[];
 extern CPU cpus_pc1512[];
@@ -89,6 +91,7 @@
 uint8_t cyrix_read(uint16_t addr, void *priv);
 
 extern int is8086;
+extern int isp5;
 
 void cpu_RDMSR();
 void cpu_WRMSR();
diff -r f18f3527baad src/model.c
--- a/src/model.c	Wed Nov 05 21:27:56 2014 +0000
+++ b/src/model.c	Sat Nov 08 23:55:25 2014 -0600
@@ -82,7 +82,7 @@
         {"AMI WinBIOS 486",     ROM_WIN486,    { "Intel", cpus_i486,    "AMD", cpus_Am486, "Cyrix", cpus_Cx486},   0,   at_ali1429_init},
 /*        {"AMI WinBIOS 486 PCI", ROM_PCI486,    { "Intel", cpus_i486,    "AMD", cpus_Am486, "Cyrix", cpus_Cx486},   0,   at_um8881f_init},*/
         {"Award SiS 496/497",   ROM_SIS496,    { "Intel", cpus_i486,    "AMD", cpus_Am486, "Cyrix", cpus_Cx486},   0,    at_sis496_init},
-        {"Award 430VX PCI",     ROM_430VX,     { "IDT",   cpus_WinChip, "",    NULL,       "",      NULL},         0,    at_i430vx_init},
+        {"Award 430VX PCI",     ROM_430VX,     { "IDT",   cpus_WinChip, "Intel",cpus_P5,   "",      NULL},         0,    at_i430vx_init},
         {"", -1, {"", 0, "", 0, "", 0}, 0}
 };
 
diff -r f18f3527baad src/p5_pipes.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/p5_pipes.h	Sat Nov 08 23:55:25 2014 -0600
@@ -0,0 +1,39 @@
+int x86canexecinv[256] = //First 256 entries are for one-byte opcodes. Next 256 are for two-byte opcodes.
+//FPU stuff isn't in here because FXCH is the only FPU instruction capable of running in the V-pipe, AFAIK.
+{
+/*0x*/  1,1,1,1,1,1,0,0,1,1,1,1,1,1,0,0,
+/*1x*/  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+/*2x*/  1,1,1,1,1,1,0,0,1,1,1,1,1,1,0,0,
+/*3x*/  1,1,1,1,1,1,0,0,1,1,1,1,1,1,0,0,
+/*4x*/  1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
+/*5x*/  1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
+/*6x*/  0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0,
+/*7x*/  1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
+/*8x*/  0,0,0,0,1,1,0,0,1,1,1,1,0,1,0,0,
+/*9x*/  1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+/*Ax*/  1,1,1,1,0,0,0,0,1,1,0,0,0,0,0,0,
+/*Bx*/  1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
+/*Cx*/  0,0,0,0,0,0,1,1,0,0,0,0,0,0,0,0,
+/*Dx*/  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+/*Ex*/  0,0,0,0,0,0,0,0,1,1,0,1,0,0,0,0,
+/*Fx*/  0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+
+//0F xx
+
+/*0x*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*1x*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*2x*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*3x*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, 
+/*4x*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*5x*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*6x*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*7x*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*8x*/ //true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
+/*9x*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*Ax*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*Bx*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*Cx*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*Dx*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*Ex*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+/*Fx*/ //false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false,
+};
\ No newline at end of file

[Alegend45]

Okay, once I got PCem to call the new execp5 function only for Pentiums, the BIOS was no longer booting. I... may have not done this right.

[SarahWalker]

I'm working on adding Pentium support as part of the recompiler, so I won't take this patch. In general, while the recompiler is still in early stages, I won't be taking any CPU related patches as the CPU changes I'm making are pretty invasive.

[Alegend45]

Ah, okay. Thanks for letting me know.