PCem v9 r304: Trident TGUI9440 text mode display corruption

[ppgrainbow]

I'm using the Trident TGUI9440 driver for the AMI WinBIOS 486 machine (Intel 80486 33MHz w/16 MB RAM, Sound Blaster 16 sound card) and since I updated to PCem v9 r304, I'm starting to notice display corruption issue when running MS-DOS 6.22 in text mode.

Have a look:

TGUI9440 text mode display corruption.png (49.73 KiB) Viewed 16470 times

I sure hope that this issue is investigated and released in the next revision.

[startmenu]

So did Mach64...

oops.png (17.85 KiB) Viewed 16457 times

ps. the rainbow logo of Energy Star has a better looking than the original one, kind of... in my point of view.

[ppgrainbow]

So did Mach64...

The attachment oops.png is no longer available

ps. the rainbow logo of Energy Star has a better looking than the original one, kind of... in my point of view.

That doesn't sound too good.

Beside that, the rainbow coloured Energy Star EPA logo sounded much better.

epa rainbow.png (2.37 KiB) Viewed 16370 times

Seriously, the Award Modular BIOS' 640 x 480 VGA display can't seem to handle more than 16 colours. LOL

[Battler]

After reading here: http://web.stanford.edu/class/cs140/pro ... extreg.htm , seems this:

O/E Page -- Odd/Even Page Select
"Selects the upper/lower 64K page of memory when the system is in an eve/odd mode (modes 0,1,2,3,7).
= 0 selects the low page
= 1 selects the high page"

needs to be emulated.

[ppgrainbow]

After reading here: http://web.stanford.edu/class/cs140/pro ... extreg.htm , seems this:

O/E Page -- Odd/Even Page Select
"Selects the upper/lower 64K page of memory when the system is in an eve/odd mode (modes 0,1,2,3,7).
= 0 selects the low page
= 1 selects the high page"

needs to be emulated.

That's what I've been thinking.

[Battler]

In addition, I just found out that the text mode renderer assumes odd/even mode is set, which it shouldn't.

Edit: Yep, making the text renderer render with attribute at address + 4 if odd/even mode is disabled fixes this issue.

[ppgrainbow]

In addition, I just found out that the text mode renderer assumes odd/even mode is set, which it shouldn't.

That's right. Text mode should NOT have odd/even mode set at all, which in doubt causes text display corruption.

[Battler]

- ppgrainbow: Actually, it varies. On standard VGA as well as S3 adapters, text mode does have odd/even mode set by default. On the other hand, adapters like the Mach64 and the Trident TVGA might not support odd/even mode at all and therefore have it turned off by default.

[ppgrainbow]

- ppgrainbow: Actually, it varies. On standard VGA as well as S3 adapters, text mode does have odd/even mode set by default. On the other hand, adapters like the Mach64 and the Trident TVGA might not support odd/even mode at all and therefore have it turned off by default.

That's what I've been thinking all along.

[SarahWalker]

Actually, the Mach64 and Trident TGUI _are_ setting odd/even mode. It's just that there are three bits controlling it (sequencer register 4 bit 2, gdc register 5 bit 4 and gdc register 6 bit 1), and they're not setting the one I was looking at.

It's quite likely actually, that on at least some graphics cards the two gdc bits are tied together.

[ppgrainbow]

Actually, the Mach64 and Trident TGUI _are_ setting odd/even mode. It's just that there are three bits controlling it (sequencer register 4 bit 2, gdc register 5 bit 4 and gdc register 6 bit 1), and they're not setting the one I was looking at.

It's quite likely actually, that on at least some graphics cards the two gdc bits are tied together.

Oh really?

The problem is that even if the Mach64 and Trident TGUI 9440 are setting odd/even mode, something could be causing the text mode display corruption and the background all green instead of black.

[Battler]

It's just that there are three bits controlling it (sequencer register 4 bit 2, gdc register 5 bit 4 and gdc register 6 bit 1), and they're not setting the one I was looking at.

Well, from what I am reading:
- Sequencer register 4 bit 2 only controls write access.

O/E Dis. -- Odd/Even Host Memory Write Adressing Disable
"When this bit is set to 0, even system addresses access maps 0 and 2, while odd system addresses access maps 1 and 3. When this bit is set to 1, system addresses sequentially access data within a bit map, and the maps are accessed according to the value in the Map Mask register (index 0x02)."

- GDC register 5 bit 4 only controls read access.

Host O/E -- Host Odd/Even Memory Read Addressing Enable
"When set to 1, this bit selects the odd/even addressing mode used by the IBM Color/Graphics Monitor Adapter. Normally, the value here follows the value of Memory Mode register bit 2 in the sequencer."

Memory Mode register bit 2 is sequencer register 4 bit 2.

So chain2 should be:
- For write: (GDC6 & 2) || !(SEQ4 & 4);
- For read: (GDC6 & 2) || (GDC5 & 0x10).

The problem is that even if the Mach64 and Trident TGUI 9440 are setting odd/even mode, something could be causing the text mode display corruption and the background all green instead of black.

Yes, that's because while the mode is set, the emulator is unaware of it, as it doesn't check everything that turns it on.

[ppgrainbow]

That's what I've been thinking all along. If the emulator doesn't check everything that it turns on, it's not going to properly handle the colours on the text mode display which in fact has resulted in text mode display corruption.

[SarahWalker]

Documentation I've sourced on this :

EGA:

Code: Select all

Memory Mode Register (Sequencer reg 4)

Bit 2	Odd/Even-A logical 0 directs even processor
	addresses to access maps 0 and 2, while odd
	processor addresses access maps 1 and 3. A
	logical 1 causes processor addresses to
	sequentially access data within a bit map. The
	maps are accessed according to the value in the
	map mask register.

Mode Register (GDC reg 5)

Bit 4	Odd/Even-A logical 1 selects the odd/even
	addressing mode, which is useful for emulation of
	the Color Graphics Monitor Adapter compatible
	modes. Normally the value here follows the value
	of the Memory Mode Register bit 3 of the Sequencer.

Miscellaneous Register (GDC reg 6)

Bit 1	Chain Odd Maps To Even Maps-When set to 1,
	this bit directs the processor address bit 0 to be
	replaced by a higher order bit and odd/even
	maps to be selected with odd/even values of the
	processor AO bit, respectively.

VGA (from PS/1 technical reference) :

Code: Select all

Memory Mode Register (Sequencer reg 4)

Bit 2	Odd/Even - When bit 2 is set to 1, the system
	microprocessor sequentially accesses data within a bit
	map. When bit 2 is set to 0, even addresses access maps
	0 and 2 and odd addresses access maps 1 and 3. The
	maps are accessed according to the value in the Map
	Mask register (index 02).

Mode Register (GDC reg 5)

Bit 4	Odd/Even - When bit 4 is set to 1, the odd/even addressing
	mode is selected, which is used for emulation of the IBM
	Color/Graphics Monitor Adapter compatible modes.
	Normally, this value follows the value of the Memory
	Mode register bit 2 (Odd/even) of the sequencer.

Miscellaneous Register (GDC reg 6)

Bit 1	Odd/Even - When bit 1 is set to 1, the system
	microprocessor address bit 0 is replaced by a
	more-significant bit and odd/even maps to be selected
	with odd/even values of the system microprocessor A0 bit,
	respectively.

Mach64 (from mach64 VGA Register Guide) :

Code: Select all

Memory Mode Register (Sequencer reg 4)

Bit 2	Odd/Even
	0 = Uses the LSB CPU address bit A0 to select which memory
	map to access. Even CPU addresses access maps 0 and 2; odd
	addresses access maps 1 and 3.
	1 = Enables sequential access to video data maps for odd/even
	modes. Map Mask register bits SEQ02[0:3] identify which maps
	are to be access for each CPU address.

Mode Register (GDC reg 5)

Bit 4	Odd/Even Addressing Enable
	Used to enable CGA emulation, this bit enables the odd/even
	addressing mode when it is logical one. Normally, this bit and
	memory mode bit SEQ04[2] are set to agree with each other in
	enabling odd/even mode emulation.

Miscellaneous Register (GDC reg 6)

Bit 1	Chain Odd Maps to Even:
	1 = CPU address bit A0 is replaced by a higher order address bit.
	Even maps (0 and 2) are selected when A0 = zero; odd maps are
	selected when A0 = one.

Based on this, I've concluded that the sequencer register bit is the one that should be used. On EGA the graphics controller ASIC doesn't have a connection to the address bus, so it must be the sequencer which determines what addresses are written, and it's fairly safe to assume that VGA implements this the same way. The Mach64 documentation makes the point of it having a 100% compatible VGA core, so it probably implements it the same way.

There also isn't any such thing as a non-odd/even text mode on VGA; in fact odd/even mode has no effect on how the VGA reads memory for display. Character codes are read from plane 0, attribute codes from plane 1, font definitions from plane 2.

[ppgrainbow]

Thank you for reading up on the documentation regarding the video adapters that you mentioned.

By the way, I'm wondering if there is a fix to the text mode display corruption when using the Trident TGUI9440 or the Mach64 video card yet? If there is, let me know.

[Battler]

- TomWalker: A good idea would be to test the whole lot on a real card and see what happens.

Though I attempted to implement the thing in the way I described and it actually fixed the problem. Specifically, I did this:

So chain2 should be:
- For write: (GDC6 & 2) || !(SEQ4 & 4);
- For read: (GDC6 & 2) || (GDC5 & 0x10).

I followed this site: http://web.stanford.edu/class/cs140/pro ... a/home.htm , which references a whole load of things, including IBM's own VGA reference.

Edit: And if the reading part was incorrect, there would be plenty of black screening in text mode when using the S3 for example, as the S3 BIOS often reads the entire text mode buffer, does a change to it, then writes it back in its entirety. It happens during Award BIOS's output shortly before booting the OS (when the big table with system details is shown), and any time DOS outputs anything.

[SarahWalker]

Okay, just tested this on an S3 ViRGE. Results :

* Clearing SEQ4 bit 2 activates odd/even on writes
* Setting GRA5 bit 4 activates odd/even on reads
* Setting GRA6 bit 1 fixes MA0 to MA13 or MA15

There are some odd effects with some combinations other than the common ones, but I think based on this SEQ4 and GRA5 are used to determine odd/even and GRA6 can be ignored.

[SarahWalker]

Implemented the above in rev 305. Seems to work on everything I tried.

[Battler]

And now you get nothing but blackness in the DOS window when switching from full screen to windowed mode with the EGA driver. :p

Edit: Nevermind, applied the patch incorrectly. Now applied it correctly, and it works fine.

[ppgrainbow]

Implemented the above in rev 305. Seems to work on everything I tried.

Yay! I updated to r305 and the TGUI9440/Mach 64 text mode display corruption is gone!

[startmenu]

Implemented the above in rev 305. Seems to work on everything I tried.

Yay! I updated to r305 and the TGUI9440/Mach 64 text mode display corruption is gone!

However a new issue related to this appears. That is, changing CPU frequency also causes Mach64(800x600x32) display corruption.

[ppgrainbow]

Implemented the above in rev 305. Seems to work on everything I tried.

Yay! I updated to r305 and the TGUI9440/Mach 64 text mode display corruption is gone!

However a new issue related to this appears. That is, changing CPU frequency also causes Mach64(800x600x32) display corruption.

Oh dear! I didn't know that this was happening. Does it affect the clock speed of the CPU frequency (MHz)? If that's the case, I'll go test it out right now.

Update: I tested it out and it doesn't happen in MS-DOS. Can you upload a screenshot for evidence?