[Patch] Undocumented instructions and processor accuracy

Greatpsycho · Post by **Greatpsycho** » Sun 23 Apr, 2017 12:24 pm

This patch does the following

- Added undocumented TEST instruction(0xF6/1 and 0xF7/1) on all processors.
- Added undocumented instruction 0xF1 as alias of LOCK prefix on 286 and ICEBP on 386+ processors.
- Implemented full features of 286 LOADALL instruction
- 286 SMSW instruction set higher 12 bits to 1 as real processor does.

omarsis81 · Post by **omarsis81** » Sun 23 Apr, 2017 8:52 pm

Wow! Great job!

Post by **SarahWalker** » Fri 28 Apr, 2017 6:06 pm

Committed at rev 699.

Greatpsycho · Post by **Greatpsycho** » Sun 30 Apr, 2017 5:00 am

This additional patch does the following

- Raise exception #6 when attempt to execute opcode 0xC6/1~0xC6/7 and 0xC7/1~0xC7/7 on 286+ processors.
- Raise exception #13 when attempt to write code segment in protected mode.
- 286 LOADALL instruction does not alter PE bit in MSW register when in protected mode.

Greatpsycho · Post by **Greatpsycho** » Mon 19 Jun, 2017 1:31 pm

This patch applies experimental 286 TSS switching. Microport UNIX System V-AT 2.3 installer no longer crashes.

Post by **SarahWalker** » Mon 19 Jun, 2017 7:10 pm

Committed at rev 777.

ecksemmess · Post by **ecksemmess** » Tue 20 Jun, 2017 10:59 am

Greatpsycho wrote:This additional patch does the following

- Raise exception #6 when attempt to execute opcode 0xC6/1~0xC6/7 and 0xC7/1~0xC7/7 on 286+ processors.
- Raise exception #13 when attempt to write code segment in protected mode.
- 286 LOADALL instruction does not alter PE bit in MSW register when in protected mode.

Sarah, did you ever apply this patch posted upthread from 30 April? The changes don't appear to be live in the repo currently. (Note: at first glance it looks like a few things in there may need to be checked to avoid regressions of other alterations that have been made to some of the same code since then)

Post by **SarahWalker** » Tue 20 Jun, 2017 5:13 pm

Apparently not! Thanks for the reminder.

Post by **SarahWalker** » Tue 20 Jun, 2017 6:47 pm

Committed in revs 778-780.

Greatpsycho · Post by **Greatpsycho** » Mon 26 Jun, 2017 2:05 pm

This patch improves task switching accuracy. Borland C++ 2.0 for 286(BCX.EXE & BCCX.EXE) and Turbo debugger for 286 no longer crashes.

Post by **SarahWalker** » Wed 05 Jul, 2017 8:55 pm

Committed at rev 785.

Greatpsycho · Post by **Greatpsycho** » Thu 06 Jul, 2017 2:22 pm

More task switching fixes. It fixes OS/2 Warp 4.0 installer crashing.

ecksemmess · Post by **ecksemmess** » Sat 08 Jul, 2017 5:40 pm

If I'm not mistaken, it looks like this last patch that fixes the OS/2 Warp 4.0 installer was committed at rev 787?

Post by **SarahWalker** » Sun 09 Jul, 2017 5:34 pm

Sorry, yes.

Greatpsycho · Post by **Greatpsycho** » Tue 11 Jul, 2017 8:58 am

This patch does the following

- LTR instruction set TSS state to busy.
- LMSW instruction does not alter ET bit in CR0 register.
- Improved accuracy destination IP address calculation in protected mode JMP and CALL instruction via system segment.

Post by **SarahWalker** » Sun 16 Jul, 2017 3:06 pm

Committed at rev 796.

SA1988 · Post by **SA1988** » Mon 17 Jul, 2017 1:35 pm

The latest commit (in x86seg.c where it says "x86ss("Load CS call not present", seg & 0xfffc);" ) breaks win3.0 in protected mode. It should be set to x86np.

Greatpsycho · Post by **Greatpsycho** » Mon 17 Jul, 2017 2:03 pm

SA1988 wrote:The latest commit (in x86seg.c where it says "x86ss("Load CS call not present", seg & 0xfffc);" ) breaks win3.0 in protected mode. It should be set to x86np.

It seems 86Box's trouble. PCem doesn't have this problem.

Battler · Post by **Battler** » Mon 17 Jul, 2017 2:28 pm

Yes, I misapplied one of your patches. I fixed the problem now.

Greatpsycho · Post by **Greatpsycho** » Fri 10 Nov, 2017 8:46 am

This patch does the following.

- Implemented IDT limit too small exception on real mode.
- Changed AT compatible machine's reset vector to F000:FFF0 instead of FFFF:0000
- Set IDT limit to 0xFFFF when system reset as real machine does.

Edit : Below feature also added.
- Changed 286 and 386SX processor's address mask to 24bit.

Edit : This patch has been incorporated here.

Greatpsycho · Post by **Greatpsycho** » Sun 19 Nov, 2017 11:35 am

This patch does the following. Reworked against rev 932.

- Implemented IDT limit too small exception on real mode.
- Changed AT compatible machine's reset vector to F000:FFF0 instead of FFFF:0000
- Set IDT limit to 0xFFFF when system reset as real machine does.
- Changed 286 and 386SX processor's address mask to 24bit.
- More fixes applied to get improved accuracy.

Edit : This patch has been incorporated here.

Greatpsycho · Post by **Greatpsycho** » Fri 24 Nov, 2017 8:38 am

This patch does the following. Reworked against rev 937.

- Implemented IDT limit too small exception on real mode.
- Changed AT compatible machine's reset vector to F000:FFF0 instead of FFFF:0000
- Set IDT limit to 0xFFFF on 286 and 0x03FF on 386+ when system reset as real machine does.
- Changed 286 and 386SX processor's address mask to 24bit.
- Correctly initialize segment descriptor cache when system reset.
- Improved accuracy of ROM BIOS mapping to top 128KB address area on 286 and 386SX processor.

Edit : This patch has been incorporated here.

Greatpsycho · Post by **Greatpsycho** » Sun 10 Dec, 2017 10:08 am

This patch does the following. Reworked against commit c014367.

- Implemented IDT limit too small exception on real mode.
- Changed AT compatible machine's reset vector to F000:FFF0 instead of FFFF:0000
- Set IDT limit to 0xFFFF on 286 and 0x03FF on 386+ when system reset as real machine does.
- Changed 286 and 386SX processor's address mask to 24bit.
- Correctly initialize segment descriptor cache when system reset.
- Improved accuracy of ROM BIOS mapping to top 128KB address area on 286 and 386SX processor.
- Don't push exception error code on stack when triple fault exception occurs.

Edit : This patch has been incorporated here.

Post by **SarahWalker** » Sun 10 Dec, 2017 10:58 am

I'm holding off on this patch until after v13 is out - I don't want to make these kind of changes this close to release.

Greatpsycho · Post by **Greatpsycho** » Sun 17 Dec, 2017 12:55 pm

This patch does the following. Reworked against version 13.1.

- Implemented IDT limit too small exception on real mode.
- Changed AT compatible machine's reset vector to F000:FFF0 instead of FFFF:0000
- Set IDT limit to 0xFFFF on 286 and 0x03FF on 386+ when system reset as real machine does.
- Changed 286 and 386SX processor's address mask to 24bit.
- Correctly initialize segment descriptor cache when system reset.
- Improved accuracy of ROM BIOS mapping to top 128KB address area on 286 and 386SX processor.
- Don't push exception error code on stack when triple fault exception occurs.

Post by **SarahWalker** » Mon 08 Jan, 2018 9:11 pm

Committed in revs 988-995.

Greatpsycho · Post by **Greatpsycho** » Sun 01 Mar, 2020 3:10 pm

This patch does the following.

- Only on 386+ processor will clear general-purpose registers on CPU soft-reset as real processor does.
- Tuned cpu_rom_prefetch_cycles value to when accessing 150ns mask-rom cycles. I think this is probably closer to real machines.

Edit : This patch has been incorporated [url=http://pcem-emulator.co.uk/phpBB3/viewtopic.php?f=5&p=13388#p13388]here[/url].

Post by **SarahWalker** » Sat 07 Mar, 2020 1:52 pm

Committed the reset change at rev 1522. I've not taken the ROM timing change for now; it will work okay for some machines but I don't think the one-size-fits-all approach will work brilliantly overall. A better approach would be to allow for per-machine ROM timings, but seeing as feature freeze is tomorrow that's probably a change for v17.

[Patch] Undocumented instructions and processor accuracy

[Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy

Re: [Patch] Undocumented instructions and processor accuracy